![]() ![]() With this unified flow, customers can focus on innovative design, rather than spending time managing disparate, error-prone toolsets," said Tom Beckley, senior vice president and general manager in the Custom IC & PCB Group at Cadence. "The comprehensive Cadence RFIC solutions cover all aspects of RF design-from RF custom passive device generation and modeling to EM-IR analysis with self-heating. "With the availability of the new PDK, those creating next-generation mobile, 5G, and wireless designs can adopt our technologies quickly and accelerate the path to advanced-node innovation." "Through our ongoing collaboration with Cadence, we’re making it easier for customers to achieve their productivity goals using the jointly developed design flow and our advanced N6RF process technology, which offers significant performance and power efficiency boosts," said Suk Lee, vice president of the Design Infrastructure Management Division at TSMC. Overall, the new Cadence RFIC full flow offers an efficient methodology that lets engineers achieve design goals-performance, power efficiency and reliability-in a single, tightly integrated design environment. Additionally, the flows offer seamless integration between the Cadence EMX ® Planar 3D Solver and the Virtuoso Layout Suite EXL implementation environment, which enables designers to streamline EM modeling tasks and leverage automation to stitch S-parameter models into the golden design schematic for RF simulations automatically.įor post-layout analysis, the S-parameter models are layered into Cadence Quantus ™ Extraction Solution results for high-fidelity RF signoff circuit and EM-IR simulations. ![]() Customers can benefit from several key features, which enable them to effectively manage corner simulations, perform statistical analyses and achieve design centering and circuit optimization. Optimized for TSMC’s N6RF process technology, the Cadence Virtuoso ® Schematic Editor, Virtuoso ADE Suite and the integrated Spectre ® X Simulator and RF option are included in the RF Design Reference Flow. ![]()
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